In this paper, we develop a matrix-based formulation for the Cyclic Redundancy Check (CRC) computation that is derived from its polynomial-based definition. Then, using this formulation, we propose a parallel CRC computation structure with optimizations specific to the case when the degree of parallelism is greater than the degree of the generator polynomial. Afterward, through extensive simulations we obtain the optimum degrees of parallelism in terms of their critical path delays for some common generator polynomials. We also show that the time-area product follows the critical path delay plot.Index Terms-Cyclic Redundancy Check (CRC), parallel hardware, error control coding.

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The cyclic redundancy check (CRC) is a popular error detection code (EDC) used in many digital transmission and storage protocols. Most existing digit-serial hardware CRC computation architectures are based on one of the two wellknown bit-serial CRC linear feedback shift register (LFSR) architectures. In this paper, we present and investigate a generalized CRC formulation that incorporates negative degree terms. Through software simulations, we identify useful formulations that result in reduced time and/or area complexity CRC circuits compared to the existing non-retimed approaches. Implementation results on an Altera field-programmable gate array (FPGA) device are reported. We conclude that the proposed approach is most effective when the digit size is greater than the generator polynomial degree.

Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach and suggest a modification to its architecture. First, we propose retiming the second step to the delay of the first step in order to obtain a parallel CRC computation architecture with minimal critical path delay. Next, we propose a software algorithm to find multiple polynomials and identify ones for some useful cases. Finally, implementations are carried out on a Xilinx Virtex-5 field-programmable gate array (FPGA) device, comparing the proposed architecture with the original. As expected, the proposed architecture demonstrates improvements in timing at the cost of additional area.

Synchronization is a critical operation required by majority of wireless receivers. This paper presents the design, implementation, and evaluation of an orthogonal frequency-division multiplexing baseband packet synchronizer deployed on a field-programmable gate array (FPGA). Packet detection, carrier frequency offset estimation/correction, and time synchronization are all performed in the time domain by processing samples before the fast Fourier transform computation on the receiver. We propose techniques to reduce the area complexity of the arithmetic computations while maintaining the performance of existing approaches. FPGA implementation results are reported, and the design is evaluated by simulation under additive white Gaussian noise channel conditions.