Experimental details concerning measurements of the deceleration of Al and Cu disks rotating under the influence of a localized, nonuniform magnetic field are discussed. For a specified magnetic field distribution, the deceleration of the disk is measured as a function of radial location of the field from the rotation axis and the magnetic drag coefficient at each point is calculated. The measured values of the drag coefficients are compared to theoretical predictions and excellent agreement is obtained.

The method of successive approximations is applied to Maxwell’s equations to calculate the magnetic drag on a conducting disk rotating under the influence of a localized nonuniform magnetic field. An expression for the damping torque produced by the magnetic field is obtained in the low-velocity (quasi-static) limit of the disk’s motion: The damping force, in the case of rectilinear motion, is also calculated. When the theoretical expression for the damping torque is specialized to the case of a uniform magnetic field, the result is found to be identical with that of an existing textbook treatment. In the Appendix, a simplified treatment of the magnetic drag problem suitable for an introductory-level laboratory class is given. This treatment yields a final expression for the damping torque which is identical in form to the rigorous result except for a scaling factor.

While transistor gate lengths may continue to shrink for some time, the semiconductor industry faces increasing difficulties to satisfy Moore’s Law. One solution to satisfying Moore’s Law in the future is to stack transistors in a 3-dimensional (3D) formation. In addition, the need for expanding functionality, real-estate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques. We describe in this paper innovations in Magnetic Field Imaging for FI which have the potential to allow 3D characterization of currents for non-destructive fault isolation at every chip level in a 3D stack.

Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.

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