As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated•제1저자 : 김용민 •교신저자 : 김종면

This paper proposes an efficient two-stage fault prediction algorithm for fault detection and diagnosis of induction motors. In the first phase, we use a linear predictive coding (LPC) method to extract fault patterns. In the second phase, we use a dynamic time warping (DTW) method to match fault patterns. Experiment results using eight vibration data, which were collected from an induction motor of normal fault states with sampling frequency of 8 kHz and sampling time of 2.2 second, showed that our proposed fault prediction algorithm provides about 45% better accuracy than a conventional fault diagnosis algorithm. In addition, we implemented and tested the proposed fault prediction algorithm on a testbed system including TI's TMS320F2812 DSP that we developed.

We address the problem of constructing classifiers of digital quadrature and offset modulated signals b y the likelihood approach and the Mth-law approach. In the first approach, we start from the likelihood functionals (LF) of such signals in additive white Gaussian noise (AWGN) and, based on these LFs, we derive easily implementable classifiers. In the second approach, Mth-law classifiers are examined for classifying such signals. It is shown that certain versions of the LF classifier are closely related to the Mth-law classifier in terms of both implementation and performance, at least in the low-SNR regime.

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The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of