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This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta-sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm 1P6M CMOS process. In view of areaefficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by [2 + (g′m3/gm1 − 1)  A] times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master-slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits-at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm 2 , and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.

This study developed a predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) with a fuzzy proportional-integral-derivative (PID) controller and a new round-off calculation circuit for improving the ripple response of a hysteresis controller when sampling and calculating delay times in an induction motor drive. The proposed PDTC ASIC not only calculates the stator's magnetic flux and torque by detecting three-phase currents, three-phase voltages, and rotor speed but also eliminates large ripples in the torque and flux by using the fuzzy PID controller. Furthermore, the proposed round-off algorithm reduces the calculation error of the composite flux. A fuzzy voltage vector switching table is proposed not only to speed up the calculating speed but also to resolve the instability generated by its large torque and flux ripples. The Verilog hardware description language was used to implement the hardware architecture, and the aforementioned ASIC was fabricated using the 0.18-μm 1P6M CMOS process of the TSMC by employing the cell-based design method. The predictive calculations, fuzzy PID controller, fuzzy voltage vector switching table, and round-off calculation algorithm improved not only the ripple issue faced in traditional direct torque control but also the control stability and robustness. The measurement results indicate that the proposed PDTC ASIC has an operating frequency, a sampling rate, and a dead time of 50 MHz, 100 kS/s, and 100 ns, respectively, at a supply voltage of 1.8 V. The power consumption and chip area of this ASIC are 1.0027 mW and 1.169 × 1.168 mm 2 , respectively. The main advantages of the proposed PDTC ASIC are its low power consumption, small chip area, robustness, and convenience.INDEX TERMS Direct torque control (DTC), Predictive calculation, fuzzy PID controller, round-off algorithm, application-specific integrated circuit (ASIC), induction motor (IM), hardware description language (HDL).

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