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cross-sectional view of SRAM cell transistor with contact landed in active region illustrating excellent For the first time, we present a state-of-the-art cnatt cieoelycnrl otc rcs 32nm low power foundry technology integrated with robust isalsodemontrate intFigurecbwt 0.15 2 6-ihdniySA,lwsadyrobustness IS also demonstrated in Figure 2b with 0.l5um 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k good Vcc and butted contact Rc distribution. interconnect for mobile SoC applications. To our Process and Transistor Performance knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors Shallow trench process is carefully optimized to with Lg of 30nm achieve current drive of 700/380 support aggressive isolation requirements in SRAM uA/um at 1.1V and off-leakage current of 1 nA/um for with superior drive current enhancement in narrow NMOS and PMOS, respectively. An NPoly/NWell MOS device. Transistors with nitrided oxide of 1.6nm are varactor shows capacitance ratio of >5.0. The MOM designed for low standby power applications. The unit capacitance of 3.5 fF/um2 is achieved with only 4 ultra-shallow junction is realized with advanced metal layers.co-implant and anneal scheme to meet aggressive junction abruptness and S/D extension resistance. Introduction PMOS ultra shallow junction using different implant and anneal schemes is evaluated and shown in Figure A suitable SoC process technology needs to 3. Co-implant with advanced anneal (MSA-2) achieved support both digital and analog functions with high ITRS roadmap of S/D Rs and Xj. density embedded memories. This paper presents a Combinations of various strain engineering leading edge platform technology, optimized for low techniques are evaluated and optimized for transistor power, high density and manufacturing margins with mobility gain. Geometric parameters such as recess optimal process complexity and cost. Competitive depth and proximity are critical for optimizing SRAM bit cells are designed and thoroughly performance gain from eSiGe process. SiGe to Poly characterized to provide the optimized process and distance has stronger impact on performance gain design margins. Asymmetric deviceswith high voltage than recess depth for smaller pitch as shown in Figure gain and I/O devices with high drain voltage tolerance 4. In Figures 5a and 5b, NMOS with optimized strain are developed to facilitate design flexibility. The BEOL process provides 10% lon-loff gain over control interconnect integration iS implemented with CU/low-k process, additional 20-30% lon-loff performance boost to balance the performance requirements in RC delay for PMOS can also be obtained with compressive and reliability. CESL. Transistor Id-Vg and Id-Vd characteristics are SRAM Patterning and Characterization shown in Figures 6a and 6b. NMOS with SMT and tensile CESL achieved Ion of 700 uA/um at loff of 1 Ultra high density SRAM cell patterning is realized nA/um and PMOS with eSiGe achieved Ion of 380 with high NA (1.2)/193...