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In this paper, a technique to use Ar ion-implantation on the p + -Si or poly-Si gate to suppress the boron penetration in p + pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5 2 10 15 cm 02 is shown to be able to sustain 900 C annealing for 30 min for the gate without having the underlying gate oxide quality degraded. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p + gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E bd ), interface state density (D it ), and charge-to-breakdown (Q bd ) on the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity. Index Terms-Ar implantation, boron penetration, p + pMOS-FET.

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