No abstract

A self-aligned complementary GaAs (CGaAs TM) technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being extended to address highspeed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9V have demonstrated power-delay products of 0.01µW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC TM-architecture microprocessor. This paper touches on the major aspects of the project, process technology, circuit design, packaging, architecture, CAD tools and software, with an emphasis on application of the CGaAs technology.

No abstract

No abstract

A 576 Mb DRAM is implemented with 16 serial links at 10.3125Gbps. Using careful memory/SerDes/package codesign, the system achieves 14.5ns latency and 24.75GByte/s read/write bandwidth. It achieves SRAM-like random access by using logic-compatible 65nm GP embedded DRAM and small 36 Kb sub-arrays with hidden refresh.