Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. The solutions implemented on FPGA lead to a high calculation rate using parallelization. We implemented the BCH code in a 3s400FG456 FPGA. In this implementation we used 15 bit-size word code and the results show that the circuits work quite well.

The paper justifies the necessity to use the hand writer identification using the feed forward neural networks. Identifying the authors of a handwritten sample using automatic image-based processing methods is an interesting pattern recognition problem with direct applicability in the legal and historic documents. Leading a worrisome life among the harder forms of biometrics, the identification of a writer on the basis of handwriting samples still remains a useful biometric modality, mainly due to its applicability in historical and the forensic field.

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This paper presents a solution to design and implement a hardware error detection and correction circuit using associative memories. This type of memory allows search of a binary value stored, having input data a partial (or modified) amount of this value. This property can be used in communication, for detection and correction of errors. In our analysis, the obtained experimental results were compared with performances of other hardware systems.

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