A transformer-based high-order output matching network is proposed for broadband power amplifier design, which provides optimum load impedance for maximum output power within a wide operating frequency range. A design methodology to convert a canonical bandpass network to the proposed matching configuration is also presented in detail. As a design example, a push-pull deep class-AB PA is implemented with a third-order output network in a standard 90 nm CMOS process. The leakage inductances of the on-chip 2:1 transformer are absorbed into the output matching to realize the third-order network with only two inductor footprints for area conservation. The amplifier achieves a 3 dB bandwidth from 5.2 to 13 GHz with +25.2 dBm peak P sat and 21.6% peak PAE. The EVM for QPSK and 16-QAM signals both with 5 Msample/s are below 3.6% and 5.9% at the output 1 dB compression point. This verifies the PA's capability of amplifying a narrowband modulated signal whose center-tone can be programmed across a large frequency range. The measured BER for transmitting a truly broadband PRBS signal up to 7.5 Gb/s is less than 10 13 , demonstrating the PA's support for an instantaneous wide operation bandwidth.

Compact power splitters designed ab initio using binary particle swarm optimization in a 2D mesh for a standard foundry silicon photonic platform are studied. Designs with a 4.8 μm × 4.8 μm footprint composed of 200 nm × 200 nm and 100 nm × 100 nm cells are demonstrated.Despite not respecting design rules, the design with the smaller cells had lower insertion losses and broader bandwidth and showed consistent behavior across the wafer. Deviations between design and experiments point to the need for further investigations of the minimum feature dimensions. Foundry fabricated silicon (Si) photonics seek to implement highly sophisticated photonic integrated circuits (PICs) at low cost by using the mature manufacturing process of microelectronics [1][2][3]. The high refractive index contrast in Si photonic platforms not only allows for compact device footprints but also makes possible device concepts that can take advantage of the strong optical confinement and scattering (e.g., grating couplers, micro-resonators, photonic crystals) [4][5][6]. The growing availability of foundry Si photonics, in combination with expanded computation capabilities for detailed electromagnetic simulations, open the opportunity to explore device designs that cannot be implemented in traditional, lower index contrast PIC platforms such as silica and compound semiconductors and are yet volume manufacturable.Device design performed by topology optimization without any a priori assumptions on the geometry has recently generated much interest [7][8][9][10]. As opposed to conventional design methodologies in which a few critical geometric parameters are tuned on a fixed geometry, topology optimization can find unexpected solutions with good performance within demanding constraints by exploring much larger parameter spaces. An example is the polarization beam splitter of [9], which had a design footprint constraint of 2.4 μm × 2.4 μm. However, usual optimization approaches (e.g., in [8][9][10]) rely on highresolution rendering of intricate geometric features, such as through electron-beam lithography, which can result in designs that are incompatible with the design rules and minimum feature sizes in foundry processes, which use deep ultraviolet (DUV) photolithography.In this Letter, we investigate foundry fabrication of an optimization designed 2 × 2 3 dB power splitter. Power splitters are a common building block in PICs and, in Si photonic platforms, are typically implemented as multimode interference (MMI) couplers, directional couplers, and adiabatic couplers. Typical footprints in a standard Si photonic platform have footprints around 39 μm × 5.2 μm for a 3 dB directional coupler and 158 μm × 4.1 μm for an MMI coupler [11]. Because power splitters may be instantiated many times in a PIC, a size reduction of the 2 × 2 splitter can save substantial circuit area. Here, we explore the design and implementation of 2 × 2 power splitters with a footprint constraint of 4.8 μm × 4.8 μm designed through optimization that accounted for the minimum ...

Integrated photonics is poised to become a billion-dollar industry due to its vast array of applications. However, designing and modeling photonic devices remain challenging due to lack of analytical solutions and difficulties with numerical simulation.Recently, inverse design has emerged as a promising approach for designing photonic devices; however, current implementations require major computational effort due to their use of inefficient electromagnetic solvers based on finite-difference methods. Here we report a new, highly-efficient method for simulating devices based on boundary integral equations which is orders of magnitude faster and more accurate than existing solvers, achieving almost spectral convergence and free from numerical dispersion. We develop an optimization framework using our solver based on the adjoint method to design new, ready-to-fabricate devices in just minutes on a single-core laptop. As a 1

AbstractAlthough the first lasers invented operated in the visible, the first on-chip devices were optimized for near-infrared (IR) performance driven by demand in telecommunications. However, as the applications of integrated photonics has broadened, the wavelength demand has as well, and we are now returning to the visible (Vis) and pushing into the ultraviolet (UV). This shift has required innovations in device design and in materials as well as leveraging nonlinear behavior to reach these wavelengths. This review discusses the key nonlinear phenomena that can be used as well as presents several emerging material systems and devices that have reached the UV–Vis wavelength range.

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