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Based on a recent market study of an important number of I 2 C devices, all fully compliant with the Philips I 2 C-bus specification, version 2.1, release January 2000, this paper introduces a detailed I 2 C-slave VLSI-architecture that incorporates all necessary features required by modern ASIC/SoC applications, except high speed mode. The design is a general purpose solution offering viable ways to controlling I 2 C-bus and highly flexible to suit any particular needs.The purpose of this paper is to provide a full description of an up-to-date I 2 C-slave FPGA implementation. All related issues, starting from the elaboration of initial specifications, till the final verifications and synthesis, are comprehensively discussed and justified. This includes all issues from basic architectural operations to final software drivers and application.The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365). The synthesis design code is technology independent and was simulated at both RTL and gate level with timing back annotation using ModelSim SE 5.8e and synthesized using both Leonardo Spectrum V2001 1d.45 and Xilinx's XST 6.1i.

Based on a recent market study of an important number of I 2 C devices, all fully compliant with the Philips I 2 C-bus specification, version 2.1, release January 2000, this paper introduces a detailed I 2 C-slave VLSI-architecture that incorporates all necessary features required by modern ASIC/SoC applications, except high speed mode. The design is a general purpose solution offering viable ways to controlling I 2 C-bus and highly flexible to suit any particular needs.The purpose of this paper is to provide a full description of an up-to-date I 2 C-slave VLSI-implementation. All related issues, starting from the elaboration of initial specifications, till the final verifications and synthesis, are comprehensively discussed and justified. This includes all issues from basic architectural operations to final software drivers and application.The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365.) The synthesis design code is technology independent and was simulated at both RTL and gate level with timing back annotation using ModelSim SE 5.8e and synthesized using both Leonardo Spectrum V2001_1d.45 and Xilinx's XST 6.1i.

No abstract