No abstract

In this paper, we investigate the interaction between a chip's power distribution network and its substrate to understand its impact on power supply noise and substrate-coupled noise. The study is set in the context of low-voltage, low-power, mixed signal chip designs based on low resistance, epitaxial process, substrate technology. We believe the findings of this study are significant to both the chip integration engineer and the analog circuit designer. We attempt here to answer two important questions: (1) To what extent can substrate modify the power supply noise, and what parameters of substrate design, if any, are salient? (2) What is the extent of coupling from the noisy digital power supply to the analog circuits through the substrate? We propose a method to simulate the power grid along with the substrate and present findings of case studies conducted on three low-power processor designs.