Electronic systems are increasingly used for safety critical applications, where the effects of fa ults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this fo llows the Branch Target Buffer (BTB) architecture; the proposed approach is fu nctional, i.e., it is based on fo rcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB.