No abstract

RECENT ADVANCES in CMOS technology have enabled CMOS static' and non-volatile memories2 t o realize power reduction, while achieving density and speed performance equal to their NMOS counterpart. Dynamic RAM, a forefront of VLSI memory development, traditionally employed NMOS dynamic on the line circuits to conserve power requirements, at the expense of chip area and design complexity. To explore the impact of CMOS technology for dynamic RAM, a third generation high performance 64K DRAM was developed on a double poly Nwell CMOS technology, with device scaling t o the CHMOS 111 level. The results promise many practical benefits for the CMOS DRAM approach.The current CMOS DRAM utilizes a P-channel memozy cell imbedded in an N-well biased a t VDD potential. The N-well array acts as an effective minority carrier barrier t o minimize soft error induced by alpha particles and to isolate the storage cells from substrate noise injected by external circuits. Inside the N-well, during device operation, the low impact ionization current of the P-channel transfer gate also contributes t o a quiet background for charge storage. Under the first poly layer, the storage gate oxide thickness is 15Oaoxide. The memory cell size is 1 3 8~2 . A Hi-C boron cell implant and compact bird's beak processing were also used to achieve an average cell capacitance of 145fF. The resulting cell structure accomodates a wide memory operating range of 3 to 7V, and eliminates the need to bootstrap the wordline. Figure 1 shows the cross-section of the memory cell and the periphery CMOS construction.The memory array is organized into four identical quadrants with a folded metal bit line and poly wordline configuration. The poly wordline delay is reduced to lOns by applying a CMOS repeater within each quadrant. During the precharge cycle, the % C reference cell is charged to VDD (5V), while the bit lines are initialized to Vss (OV) via the N-channel precharge transistors. Sensing is accomplished by a clocked P-channel cross-coupled latch. Bit lines are actively restored by a set of N-channel latches. Figure 2 shows the array circuit schematics along a pair of bit lines.In the area of periphery design, CMOS static circuits have reduced the number of clock generators required in a conventional NMOS DRAM by a factor of three. Figure 3 shows the CMOS address buffer circuit to illustrate the design simplicity. Clocked CMOS circuits are also used in decoders and operation synchroni--'Minato, O., et. a l . , "A Hi-CMOS I1 8 K x 8K Static RAM", ISSCC DIGEST O F T E C H N I C A L P A P E R S ,p. 256-257; Feb.. 1982. N-Well Technology", ISSCC DIGEST OF TECHNICAL 'Miyasaka, K., e . d . , "A 150ns CMOS 64K EPROM Using PAPERS, p. 182-183; Feb., 1982.zation. Table 1 compares the periphery circuit design complexity between the current 64K CMOS DRAM and a NMOS version. The reduction of the random periphery overhead in the CMOS DRAM improves the ratio of memory array to total active die area to 50%. Figure 4 shows the die photograph. The die size is 30464 mil2. Redund...