Abstract-A new algorithm for parallel fault simulation of VLSI on multicore workstations with common memory is proposed. To speeding up the algorithm two-level parallelization is used. First, main schema of the algorithm is based on the concurrent many-threaded simulation of the groups of faults for each input vector. Second, each group of faults is simulated in bit-parallel way. The dynamic fault grouping is adopted. The results of computational experiments on ISCAS-89 benchmarks circuits are reported, which are obtained on the 12-core workstation.

The parallel genenic algorithms are considered for problem of test generation. The different forms of parallelization of genetic algorithms are investigated for test generation.

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