Low-and high-barrier Schottky diodes have been combined with bipolar transistors to produce planar integratedcircuit low-area memory cells that hold at 75 ,aW. Low-barrier diodes formed on p-type ion-implanted silicon (10'T cm-') are used as high-resistance collector loads. High-barrier diodes formed on n-type epitaxial silicon (1016 cm-8) provide low-capacitance low-Ieakage coupling to digit lines in a memory array.The highly reproducible rho&lum silicide on s~lcon Schottky diodes, as well as high-quality otilc contacts, are formed in one sequence of sputtering and high-temperature operations. The process is fully compatible with beam-lead technology. It is estimated that a 5K?-word memory module using these cells would operate at a 60-ns READor WRITEcycle time.

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A 16K MASK PROGRAMMABLE ROM has been fabricated, using a standard bipolar technology, with a Schottky diode as the cell. The circuit features an access time of 150ns at 165mW dissipation.A Schottky diode was chosen as the cell because it is the smallest circuit element (cell area = 0.65 mil2) that can be fabricated with conventional bipolar IC technology, and the resultant array is frce of the emitter-collector leakages that often limit yield of bipolar circuits. Yield is also enhanced by employing a majority coding scheme which allows any program to be coded with less than 8K Schottky windows.The Cell Array Figure 1 shows the basic cell array and Figure 2 illustrates the corresponding layout. A bit is addressed by the coincidence of sinking current from a bit line and forcing voltage on a word line. If a Schottky diode is present at the intersection, the bit line will be held high, b u t if no diode is formed, the bit line will be pulled low. of its basic simplicity and high packing density. To maintain processing simplicity, single level metal is employed, but this creates a design challenge since the bit line consists of only the N+ emitter diffusion rails. This results in a total bit-line resistance of 5000R, and that resistance, in combination with the rail The triple-diffused GIMIC-0' technology was chosen because BIT LINE BIT LINE\ n PLUG / \ n PLUG / FIGURE 2 -Cell layout and structure.capacitance, sets the primary limitation on access time. Two level metal techniques would, of course, significantly improve circuit speed. Access Circuitry and Majority CodingBecause of the large RC time constant associated with the bit lines, access circuitry is largely ECI, to maintain small, wellcontrolled signal swings on the bit lines. This circuit choice also facilitates the majority coding scheme, where the total number of 1's and 0's are counted and the majority sense is assigncd t o the absence of a Schottky diode. In this way, less than 8K Schottky windows are required for any program. Performance and SummaryFigure 3 is a photomicrograph of the 16K ROM. The level of circuit performance attained and the small cell size are directly attributable to the choice of a Schottky diode cell; with the modest layout tolerances used, this ROlLI occupies 23,000 mil2.The chip is packaged in a standard 24 pin DIP and operates from a single 5V supply with an access time of l50ns at a total dissipation of 165mW. Three programmed chip-enable inputs are provided for 1/8 chip selection, and although internal ECL circuits arc used, the outputs are tri-state TTJ,, and all inputs are low current (<2pA) TTL/NMOS compatible. BITBIT LINE LINE FIGURE 1 -Schottky diode cell array.

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