Abstract-As the performance of digital signal processors has increased rapidly during the last decade, there is a growing interest to replace the analog controllers in low power switching converters by more complicated and flexible digital control algorithms. Compared to high power converters, the control loop bandwidths for converters in the lower power range are generally much higher. Because of this, the dynamic properties of the uniformly-sampled pulse-width modulators used in low power applications become an important restriction for the maximum achievable bandwidth of control loops. After the discussion of the most commonly used uniformly-sampled pulsewidth modulators, small-signal frequency-and Laplace-domain models for the different types of uniformly-sampled pulse-width modulators are derived theoretically. The results obtained are verified by means of experimental data retrieved from a test setup.

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Abstract-When a 'classical' current control scheme is applied, the input current of a boost power factor correction (PFC) converter leads the input voltage, resulting in a nonunity fundamental displacement factor and in important zerocrossing distortion in applications with a high grid frequency (e.g. 400Hz power systems on commercial aircraft). To resolve this problem, a current-control scheme is proposed using duty-ratio feedforward. In this paper, the input impedance of the boost PFC converter for both the classical current-loop controller and the controller using duty-ratio feedforward are derived theoretically. A comparison reveals the advantages of the proposed control scheme: a low total-harmonic-distortion (THD) of the input current, a resistive input impedance, virtually no zero-crossing distortion and a fundamental displacement power factor close to unity. The theoretical results obtained are verified using an experimental setup of a digitally controlled boost PFC converter.

Abstract-As the performance of digital signal processors has increased rapidly during the last decade, there is a growing interest to replace the analog controllers in low power switching converters by more complicated and flexible digital control algorithms. Compared to high power converters, the control loop bandwidths for converters in the lower power range are generally much higher. Because of this, the dynamic properties of the uniformly-sampled pulse-width modulators used in low power applications become an important restriction to the maximum achievable bandwidth of control loops. Though frequency-and Laplace-domain models for uniformly-sampled pulse-width modulators are very valuable as they improve the general perception of the dynamic behavior of these modulators, the direct discrete design of the digital compensator requires a zdomain model for the combination modulator and converter. For this purpose a new exact small-signal z-domain model is derived. In accordance with the zero-order-hold equivalent commonly used for 'regular' digital control systems, this z-domain model gives rise to the development of a uniformly-sampled pulse-widthmodulator equivalent of the converter. This z-domain model is characterized by its capability to quantify the different dynamics of the converter for different modulators, its ease of use and its ability to predict the values of the control variables at the true sampling instants of the real system.

Digital control of a boost power factor correction (PFC) converter requires sampling of the input current. As the input current contains a considerable amount of switching ripple and high frequency switching noise, the choice of the sampliig instant is very important.To avoid aliasing without employing a (very) high sampling frequency, the sampling is synchronized with the pulse width modulation (PWM). Sampling algorithms employing this technique successfully reject the input current ripple but are not immune to the high frequency switching noise present on all sampled signals. Therefore, a new sampling algorithm, intended for center-based or symmetric PWM, is deduced with as most important features: switching noise immunity, straighfforwardness, accurate measurement of the averaged input current and the need for only few processor cycles. The operating principle, design issues and a theoretical study of the input current error induced by the sampling algorithm due to sampling instant timing errors are derived. All theoretical results are validated experimentally by using a digitally controlled boost PFC converter switching at 50kHz.