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The transition from power systems dominated by synchronous machines to systems based on converter-based generation technologies (CGTs), is weakening currently robust power systems by reducing system inertia with the replacement of synchronous generators with low-inertia CGTs. From a frequency stability viewpoint, this is resulting in faster frequency dynamics and more frequent and larger frequency excursions after system contingencies, thus significantly affecting the stability of power systems dominated by CGTs, requiring detailed stability assessments to ensure the secure integration of CGTs. In this paper, a practical framework is presented for frequency stability studies based on time domain simulations of power systems with CGTs. A fundamental part of the proposed approach is the use of a filter to first identify worst-case scenarios among various possible system operating conditions. Once these worst-case scenarios are identified, a clustering technique is used to select representative worst-case operating conditions to evaluate the frequency stability of the system using time-domain simulations. The effectiveness of the proposed framework is demonstrated on the Chilean Northern Interconnected System (NIS), where it is shown that the proposed filter is able to quickly identify worst-case scenarios for further study. Moreover, we show that the selected representative operating conditions cover a wide-range of worst-case frequency responses, demonstrating the effectiveness of the proposed tool for frequency stability analyses.

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Power consumption is an important constraint in the design of battery-operated embedded systems. Minimizing power dissipation may be handled in terms of hardware or software optimizations. Source code-level optimization techniques have been used as an alternative to achieve low power consumption when programming embedded systems. However these techniques should be analyzed with statistical sound methods in order to reach strong conclusions about their real impact on power consumption. In this work, source code optimizations were applied on a set of representative benchmarks for embedded processors (MiBench) to analyze whether the techniques have or not an effect on power dissipation of a set of microprocessorbased platforms. Design of experiments techniques (DOE) and analysis of variance (ANOVA) were used to achieve statistical sound conclusions. Results showed that not all optimizations have a significant effect on power consumption, moreover some techniques depend on the target platform where they are run.