In this work, we have characterized a variety of SiC devices (firstand second-generation 1200 V SiC MOSFETs and 1200 V SiC JFETs) with regards to threshold voltage shifts and leakage currents at high temperatures under both static and dynamic gate bias stress conditions. It was found that, although the stability of SiC MOSFETs has increased dramatically from the first-to the second-generation due to an increase in the quality of the gate oxide layer, SiC JFET devices (which lack a gate oxide altogether) are much more stable with respect to ΔV T for both types of gate bias stresses at high temperatures. We have also characterized the interface trap density (D IT ) in SiC MOSFETs based solely on changes in the sub-threshold slope of the devices' I-V curves under elevated temperature and bias stress, and have produced ∆D IT profiles showing relative changes in interfacial defect concentration at energy levels referenced to the calculated surface potential at the threshold voltage. We have found that the defect density of second-generation SiC MOSFETs is almost an order of magnitude lower than similar first-generation devices from the same manufacturer, consistent with the decreased V T shifts seen in voltage/temperature stress experiments.