and PMOS (AQi is negligible. However, AVfb does not reach OV We report here for the first time that Fermi pinning at the because Si-Hf and Si-0-Hf bonds co-exist at the polySi interface. The polySilmetal oxide interface causes high threshold voltages in AVfb saturation value depends only on the bond number ratio. A MOSFET devices. Results indicate that pinning occurs due to the comparison of AVfb for HfOz (ALD or MOCVD) and HfSixOy interfacial Si-Hf and Si-0-AI bonds for HfO, and AIzO,, respectively. (MOCVD) films deposited with different precursors and dopant This fundamental characteristic also affects the observed polySi activation anneals produce, the universal curve in Fig. 11. The slight depletion. Device data and simulation results will be presented. variation in AVb for Hf02 can be attributed to differences in Keywords: Hf02, AI203, Fermi pinning, polYd, gate dielectric. processing conditions. Our data indicates that the shifts of Vfb(n+) INTRODUCTION and Vfb(pt) from the characteristic values for SiO, NMOS and Scaling MOSFETs to improve performance results in PMOS are a fundamental characteristic of the PolySilMeOx interface. higher gate leakage as the SiOz gate melectic becomes thinner. To These shifts are responsible for the observed high Vts. address this issue, there has been much interest in hafnium-based The impact of the sub-monolayer HfOz on the CETacc is dielectrics as a potential gate dielectric [1-3]. Two major issues shown in Figs. 12 and 13. Although the p+ gate CETacc increases evident in numerous publications [1-3] that must be addressed to with each subsequent cycle, the n+ gate has a CETacc minimum at IO fabricate useful devices for CMOS circuit applications are (1) the cycles, The n+ gate is in depletion and the minimum indicates Si-Hf high threshold voltages and (2) the large CETinv difference between bonds reduce the polySi depletion. To investigate this further, CMOS NMOS and PMOS. To date, a PolySiIMeOx CMOS process with devices were fabricated (Fig. 14). The polySi depletion for ntgate acceptable Vts for both NMOS and PMOS has not been reported. NMOS (p+ gate PMOS) is decreased (increased) when SiOz is capped Defects and charge within the gatestack (Fig. I ) can result with HfO,. This tradeoff in polySi depletion is attributed to Fermi in substantial Vt shifts. At the top interface, Fermi pinning is a pinning near (Fig. 8). Less band bending occurs for n+ polySi mechanism known to cause high Vts for metal gates [41. Considering because the polySi interface is pinned close to the bulk polySi Fermi the polySi/MeOx interface shown in Fig. 2, the question arises, 'Are level. For p+ gates, more band bending occurs because the interface is the metal atoms at the interface part of the dielectric or part of the pinned further away from the bulk. This effect occurs for low and gate electrode?' This raises the issue as to whether the interface bonds high temperame activation anneals (Fig. 15). This effect is the likely affect the Vt. In this work, we examine the role of the polySiIMeOx cause...

Hafnium oxide (HfO 2 ) is one of the most promising high-k materials to replace SiO 2 as a gate dielectric. Here we report material and electrical characterization of atomic layer deposition ͑ALD͒ hafnium oxide and the correlations between the results. The HfO 2 films were deposited at 200, 300, or 370°C and annealed in a nitrogen ambient at 550, 800, and 900°C. Results indicate that deposition temperature controls both the material and the electrical properties. Materials and electrical properties of films deposited at 200°C are most affected by annealing conditions compared to films deposited at higher temperatures. These films are amorphous as deposited and become polycrystalline after 800°C anneals. Voids are observed after a 900°C anneal for the 200°C deposited films. The 200°C deposited films have charge trapping and high leakage current following anneals at 900°C. The 300°C deposited films have lower chlorine content and remain void-free following high-temperature anneals. These films show a thickness-dependent crystal structure. Annealing the films reduces leakage current by four orders of magnitude. Finally, films deposited at 370°C have the highest density, contain the least amount of impurities, and contain more of the monoclinic phase of HfO 2 than those deposited at 300 and 200°C. The best electrical performance was obtained for films deposited at 370°C.

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The impact of Zr addition on microstructure of HfO2 after high temperature processing was investigated using Rutherford backscattering, x-ray diffraction (XRD), transmission electron microscopy, and atomic force microscopy (AFM). The ZrO2 content in the films was varied from ∼25% to 75%. XRD analysis shows that adding >50% ZrO2 leads to partial stabilization of tetragonal phase of the HfxZr1−xO2 alloy. AFM images revealed smaller grains with Zr addition. Conducting AFM showed more uniform and tighter tunneling current distribution in HfxZr1−xO2 compared to HfO2. Constant capacitance-voltage stressing performed on HfO2 and HfxZr1−xO2 metal-oxide-semiconductor capacitors indicated reduced charge trapping with Zr addition.

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