Flip chip technology has rapidly progressed in concert with the high speed and small dimension trends in electronic devices. The bump interconnects design dominates the performance of a flip chip package. This study produced a new strategy to optimize the geometric design parameters of the bump from the electrical standpoint. The first incident voltage was employed as the optimization objective function in order to reduce the response time delay in the binary command as well as maintain the chip level efficiency. Genetic algorithms were used for the search routines to evaluate the best bump geometric solutions. Two cases, 1.5 V and 3.3 V power supply voltage, were adopted to conduct this research in both air and underfill environments. The results show that the standoff height and the bump pitch determined in the underfill environment are greater than in the air environment. As the power supply voltage increases, the standoff height and bump pitch become more significant. A powerful optimal window for bump design parameters is thus established.