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RadHard-by-Design has been advanced by embedding EDAC into a 16Mbit SRAM to harden the SRAM against single event upset. Conventional RadHard-by-Design techniques are used for the non-memory circuitry. The estimated uncorrectable double bit error rate is 2.9 x 10-16 errors/bit-day assuming a geosynchronous orbit, the Adam's 90% worst case environment and a nominal 312 kHz scrub frequency. The device is SEL immune to a LET of 105 MeV-cm2/mg and TID hard to greater than 100 krad(Si).

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