Reinforcement learning is promising as a machine learning paradigm in edge computing. However, its high computational cost poses a challenge when implementing in devices with limited circuit resources and power consumption. In this study, we investigated the relationship between the bit-length of floating-point operations and the learning performance of the reinforcement learning algorithm. In the case of the FrozenLake maze problem, we found that the learning performance of 8-bit floating-point arithmetic decreased, while that of 16-bit floating-point arithmetic was comparable to that of 64-bit CPU arithmetic. Our results provide a practical guideline for designing a dedicated reinforcement learning hardware with minimum circuit resources and power consumption.

Neuromorphic engineering is a promising computing paradigm in next-generation information and communication technology. In particular, spiking neural networks are expected to reduce power consumption drastically owing to their event-driven operation. The spike-timing-dependent plasticity (STDP) rule, which learns from local spike-timing differences between spiking neurons, is a biologically plausible learning rule for spiking neural networks (SNNs). In this study, we designed and simulated an analog circuit that reproduces the multiplicative STDP rule, which is more flexible and adaptive to external signals. We also derived analytical expressions for the behavior of the proposed circuit. These results provide important insights for designing energy efficient neuromorphic devices for applications including edge computing.