The current industry trend is towards using Commerciallyavailable Off-The-Shelf (COTS) based multicores for developing realtimeembedded systems, as opposed to the usage of custom-madehardware. In typical implementation of such COTS-based multicores,multiple cores access the main memory via a shared bus. This oftenleads to contention on this shared channel, which results in an increaseof the response time of the tasks. Analyzing this increased responsetime, considering the contention on the shared bus, is challengingon COTS-based systems mainly because bus arbitration protocolsare often undocumented and the exact instants at which the sharedbus is accessed by tasks is not explicitly controlled by the operatingsystem scheduler; they are instead a result of cache misses. This paperproposes three contributions towards analyzing tasks scheduled onCOTS-based multicores. Firstly, we describe a method to model thememory access patterns of a task. Secondly, we apply this model toanalyze the worst-case response time for a set of tasks. Finally, thispaper describes a method to experimentally obtain the parametersrequired for such an analysis, by using performance monitoringcounters. We compare our work against an existing approach andshow that our approach outperforms it by providing tighter upperboundson the number of bus requests generated by the tasks.

Abstract-Next generations of compute-intensive real-time applications in automotive systems will require more powerful computing platforms. One promising power-efficient solution for such applications is to use clustered many-core architectures. However, ensuring that real-time requirements are satisfied in the presence of contention in shared resources, such as memories, remains an open issue.This work presents a novel contention-free execution framework to execute automotive applications on such platforms. Privatization of memory banks together with defined access phases to shared memory resources is the backbone of the framework. An Integer Linear Programming (ILP) formulation is presented to find the optimal time-triggered schedule for the on-core execution as well as for the access to shared memory. Additionally a heuristic solution is presented that generates the schedule in a fraction of the time required by the ILP. Extensive evaluations show that the proposed heuristic performs only 0.5% away from the optimal solution while it outperforms a baseline heuristic by 67%. The applicability of the approach to industrially sized problems is demonstrated in a case study of a software for Engine Management Systems.

No abstract

No abstract

The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core platforms. However, real-time applications have not been able to fully benefit from this transition, as the computational gains offered by multi-cores are often offset by performance degradation due to shared resources, such as main memory. To efficiently use multi-core platforms for real-time systems, it is hence essential to tightly bound the interference when accessing shared resources. Although there has been much recent work in this area, a remaining key problem is to address the diversity of memory arbiters in the analysis to make it applicable to a wide range of systems. This work handles diverse arbiters by proposing a general framework to compute the maximum interference caused by the shared memory bus and its impact on the execution time of the tasks running on the cores, considering different bus arbiters. Our novel approach clearly demarcates the arbiter-dependent and independent stages in the analysis of these upper bounds. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to the contention for the bus. We show that the framework addresses the diversity problem by applying B Dakshina Dasari 123 Real-Time Syst it to a memory bus shared by a fixed-priority arbiter, a time-division multiplexing (TDM) arbiter, and an unspecified work-conserving arbiter using applications from the MediaBench test suite. We also experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.