The effects of a novel, low-temperature (< 200 o C) PECVD TEOS SiO process on via step coverage and blanket film electrical performance are investigated and compared with a traditional PECVD SiH 4 process at similar deposition temperatures. The PETEOS process provides > 2.5x via sidewall coverage than the PE-silane based process in medium-high aspect ratio vias and also exhibits superior electrical characteristics at these temperatures, with measured electrical leakage values < 1E-7 at 2 MV.cm -1 and electrical breakdown electric field > 10 MV.cm -1 . Successful Cu plating results of via test structures are also shown.

No abstract

No abstract

No abstract