In this paper we present a control theory approach to stabilize the throughput of threads for real-time applications on a multithreaded processor. We use a statistical model of a superscalar, multi-threaded processor as transfer function to calculate the resulting IPC rate. Our control theory approach is not limited to a specific processor and can be adapted to different microprocessor architectures. We are able to guarantee a minimum IPC rate within a defined convergence interval.Furthermore our results provide a method to improve WCET analysis, because inaccuracies of the processor model are soften by the use of our control theory approach.

In this paper we model a thread's throughput, the instruction per cycle rate (IPC rate), running on a general microprocessor as used in common embedded systems. Our model is not limited to a particular microprocessor because our aim is to develop a general model which can be adapted thus fitting to different microprocessor architectures. We include stalls caused by different pipeline obstacles like data dependencies, branch misprediction etc. These stalls involve latency clock cycles blocking the processor. We also describe each kind of stall in detail and develop a statistical model for the throughput including the entire processor pipeline.

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Since most modern microprocessors are optimized for good average performance, their worst case performance is hard to predict. Therefore, the in time execution of real-time threads at any time is difficult to guarantee. So, in this paper we present an adaptive real-time microprocessor, which is fitted with a closed control loop. The controller is aware of the loss of performance due to various latency causing events at runtime and is able to respond to them by adapting the aimed throughput of each running thread. Afterwards, we evaluate our microprocessor with an embedded benchmark, discuss different parameters of the controller and show that a well-defined performance can be guaranteed by the use of control theory.

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