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Nowadays envelope tracking (ET) is considered one of the most appealing techniques for the efficiency enhancement of RF power amplifiers (PAs), but it also introduces a number of additional challenges for the system simulation and implementation. In this context, this paper aims to provide a new behavioral model capable of an improved performance when used for the modeling and predistortion of RF PAs deployed in ET transceivers. The proposed solution consists in a 2D behavioral model having as a dual-input the PA complex baseband envelope and the modulated supply waveform, peculiar of the ET case. The model definition is based on binomial series, hence the name of memory binomial model (MBM). The MBM is here applied to measured data-sets acquired from an ET measurement set-up. When used as a PA model the MBM showed an NMSE (Normalized Mean Squared Error) as low as -40 dB and an ACEPR (Adjacent Channel Error Power Ratio) below -51 dB. The simulated predistortion results showed that the MBM can improve the compensation of distortion in the adjacent channel of 5.8 dB and 5.7 dB compared to a memory polynomial predistorter (MPPD). The predistortion performance in the time domain showed an NMSE improvement of 2.5 dB against the MPPD.

This paper presents a process, voltage and temperature (PVT) compensation method for a cascode modulated polar power amplifier (PA). It is shown that it is possible to create a baseband replica circuit of the PA that has the same AM-AM nonlinearity as the PA itself. The replica circuit, that represents a transistor level model (empirical model) of the cascode modulated PA, is utilized in a PA analog predistorter. The analog predistorter linearizes and compensates for PVT variation of the cascode modulated PA. The empirical model is placed in the negative feedback of an operational transconductance amplifier. The predistorted varying envelope signal is applied to the cascode gate of the PA. It is shown that the proposed PVT compensation technique significantly reduces the PVT spread of the PA linearity indicators and improves the PA linearity. Simulations were performed in a 0.13 CMOS process.