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The problem of evaluating the limit performances of cascaded single-ended multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of optimal design curves (ODC's) which express the best (maximum optimal) noise-gain tradeoff that can be achieved -at each operating frequency -when a simultaneous constraint on amplifier input VSWR is accounted for.

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In this work, an attempt is made toward the development of a systematic design method for the performancedriven dimensioning of the various elements comprising the structure of modern transistor-based microwave injectionlocked oscillators with transmission-type topologies (TILOs). The proposed approach is based on the use of appropriate diakoptics of the various circuit blocks into a matched environment, and their behavioral modeling in the fundamentalfrequency dynamical complex envelope domain with the help of standard circuit and E.M. simulation CAD tools. This will permit, in the end, to obtain closed-form expressions for the main TILO performances in terms of the design parameters, thus permitting their optimization as a function of system-level specifications. The practical validity of the method developed was tested by designing and building a single transistor 10.75GHz core-TILO with a wide locking bandwidth (>4MHz) at the low nominal input power level targeted (-20dBm).