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Here, direct correlation between the microstructure of InAs nanowires (NWs) and their electronic transport behavior at room temperature is reported. Pure zinc blende (ZB) InAs NWs grown on SiO2/Si substrates are characterized by a rotational twin along their growth‐direction axis while wurtzite (WZ) InAs NWs grown on InAs (111)B substrates have numerous stacking faults perpendicular to their growth‐direction axis with small ZB segments. In transport measurements on back‐gate field‐effect transistors (FETs) fabricated from both types of NWs, significantly distinct subthreshold characteristics are observed (Ion/Ioff ∼ 2 for ZB NWs and ∼104 for WZ NWs) despite only a slight difference in their transport coefficients. This difference is attributed to spontaneous polarization charges at the WZ/ZB interfaces, which suppress carrier accumulation at the NW surface, thus enabling full depletion of the WZ NW FET channel. 2D Silvaco‐Atlas simulations are used for ZB and WZ channels to analyze subthreshold current flow, and it is found that a polarization charge density of ≥1013 cm−2 leads to good agreement with experimentally observed subthreshold characteristics for a WZ InAs NW given surface‐state densities in the 5 × 1011–5 × 1012 cm−2 range.

Image analysis and numerical simulation algorithms are introduced to analyze the micro‐structure, transport, and electrochemical performance of thin, low platinum loading inkjet printed electrodes. A local thresholding algorithm is used to extract the catalyst layer pore morphology from focused ion beam scanning electron microscopy (FIB‐SEM) images. n‐point correlation functions, such as auto‐correlation, chord length, and pore‐size distribution are computed to interpret the micro‐structure variations between different images of the same catalyst layer. Pore size distributions are in agreement with experimental results. The catalyst layer exhibits anisotropy in the through‐plane direction, and artificial anisotropy in the FIB direction due to low slicing resolution. Microscale numerical mass transport simulations show that transport predictions are affected by image resolution and that a minimum domain size of 200 nm is needed to estimate transport properties. A micro‐scale electrochemical model that includes a description of the ionomer film resistance and a multi‐step electrochemical reaction model for the oxygen reduction reaction is also presented. Results show that the interfacial mass transport resistance in the ionomer film has the largest effect on the electrochemical performance.

Epitaxial growth of vertical GaAs nanowires on Si(111) substrates is demonstrated by metal-organic chemical vapor deposition via a vapor-liquid-solid growth mechanism. Systematic experiments indicate that substrate pretreatment, pregrowth alloying temperature, and growth temperature are all crucial to vertical epitaxial growth. Nanowire growth rate and morphology can be well controlled by the growth temperature, the metal-organic precursor molar fraction, and the molar V/III ratio. The as-grown GaAs nanowires have a predominantly zinc-blende crystal structure along a <111> direction. Crystallographic {111} stacking faults found perpendicular to the growth axis could be almost eliminated via growth at high V/III ratio and low temperature. Single nanowire field effect transistors based on unintentionally doped GaAs nanowires were fabricated and found to display a strong effect of surface states on their transport properties.