The development of a new silicon-on-glass (SiOG) substrate and device technology is presented. The SiOG material technology consists of anodic bonding and an implant-induced separation to transfer a single crystalline silicon film onto a glass substrate. The silicon-glass interface region is characterized by an ultra-strong and thermally stable bond, and includes an in situ barrier layer that is free of mobile ions. The fabrication and analysis of CMOS devices fabricated on the SiOG substrate are also presented. The SiOG devices are comparable to those fabricated on SOI (SIMOX) wafers with respect to carrier mobility and off-state leakage current. One application for this SiOG technology is the potential integration of high performance circuits and added functionality for mobile display systems.

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Development of integrated electronics on the silicon-on-glass (SiOG) substrate is presented. The SiOG material technology, under development by Corning Incorporated, consists of anodic bonding and an implant-induced separation to transfer a single crystalline silicon film onto a glass substrate. The silicon-glass interface region is characterized by an ultra-strong and thermally stable bond, and includes an in situ barrier layer that is free of mobile ions. Key aspects of the low temperature (< 600 {degree sign}C) CMOS device fabrication process are described, with an emphasis on the design tradeoffs involved to maintain process simplicity (i.e. 6-level mask count, and no VT adjustment). The discussion also provides specific details of the device structure and operation, including mechanisms that compromise device performance identified through electrical simulation.

A major area of research for integrated electronic systems is the development of systems on glass or plastic. These alternative substrate materials impose significant constraints on electronic device fabrication, including limitations on chemical and thermal processes. This work presents an investigation on the activation of ion-implanted dopants without using the high temperature processes of conventional CMOS. The annealing temperature applied was 600°C, which could potentially enable integrated microelectronics on high-quality glass. Additional factors studied included the annealing technique (furnace or rapid thermal processing), and the use of pre-amorphization implants. Ion-implant modeling along with SIMS and SRP data was used to develop a comprehensive understanding of the experimental results. The performance of transistors fabricated with low-temperature constraints on both bulk silicon and thinfilm SOI will be presented. Index Terms-low temperature dopant activation, thin film transistors (TFTs), pre-amorphization, solid phase epitaxy (SPE)

Theoretical analysis is made for thin-film-based, 200- and 100-GHz narrow bandpass filters with respect to the intensity response as well as to the chromatic dispersion. The results indicate that the narrower the passband, the higher the chromatic dispersion. The maximum chromatic dispersion appears at the edges of the 0.5-dB passband, owing to the fast change of the group delay in the region. The deviation of chromatic dispersion induced by manufacturing error is simulated. Effective-medium approximation layers are added to simulate the contribution of surface roughness and the mixture interfaces to the passband ripple as well as the chromatic dispersion. The simulations are compared with the experimental results. The measured chromatic dispersion matches the general trend of the theoretical calculation. The imperfect surface and layer mismatch induce additional ripples across the 0.5-dB passband. The maximum chromatic dispersion within a 0.5-dB passband is 20.7 and 54.9 ps/nm for 200- and 100-GHZ narrow bandpass filters, respectively.