This paper deals with the diagnosis of eld programmable interconnect systems (FPIS) in which nets are c onnected through programmable switches arranged in grids. A hierarchical approach to diagnosis is proposed. The conditions by which such process yields full diagnosis and the characteristics of the programming sequence, are fully proved. For a FPIS consisting of a k k grid array, the number of tests is given by 4 + 4 kn 2 , while the number of programming steps is 4nk + 1 , where n is the dimension of a grid The application of this technique to commercially available FPIS in FPGAs, is discussed.

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This paper presents a combined approach for testing logic and routing resources in programmable logic devices (PLDs). The proposed approach is based on configuring the PLD using different arrangements such a s built-in self-test schemes (for ezample, a parity chain) and one-dimensional arrays (with and without common inputs). It is proved that the proposed approach achieves 100% fault coverage under a fault model consisting of a single fault in the logic resources and active routing devices, or multiple faults in the interconnection channels and input/output lines. 1: IntroductionIn the last few years, research in programmable chips such as field programmable gate arrays (FPGAs) has experienced a tremendous growth [lo]. An area which only recently has been investigated, is testing and diagnosis. For logic resources, two approaches can be distinguished: the B E T (Built-In Self-Test)-based approach of [3] and the array-based approach of [4,9]. However, both these approaches are applicable t o FPGAs and to logic resource testing only; it has been reported that in a VLSI chip of this nature, the most likely place for a fault is the interconnect [6,10]. An extensive literature exists for interconnect testing and diagnosis [1,2]. However, the issue of testing a programmable chip and its interconnect (complete testing) has not been addressed. A family of logic devices which has not been analyzed in depth is the so-called PLD (programmable logic device) [8] A PLD consists of sophisticated routing resources which connect very simple logic resources (usually the basic cell is made of a LUT with few input variables and a sequential element).The objective of this paper is to propose a methodology for complete PLD testing (both logic and interconnect resources); this methodology exploits BIST and array-based arrangements (such as proposed in [3,9] for testing logic resources) combined with a walking test set for multiple fault detection in the interconnect channels and lines. 2: ReviewTesting of logic resources in FPGAs has been dealt using two different approaches. The approach of [3] utilizes a BET-based technique, in which the logic resources are configured as units under test, test generators and verifiers.[9] has presented a new approach for testing FPGAs by utilizing their programmable and reconfiguration capabilities.For faults in the interconnect it is commonly postulated that every net can be shorted to any other net [1,2]. The Counting Sequence Algorithm of [2] can be used to detect all bridge faults with a test length of log, n where n is the number of nets. The walking test set proposed by [l] (walking-1) can be used to diagnose all bridge, stuck-at and open faults in the nets; the test set is a sequence '