:The Digital Signature Algorithm (DSA) was l~Oposed in 1991 by the US National Institute of Standards and Technology to provide an appropriate core fur applications requiring digital signatures. Undoubtedly, many applications will include this standard in the future and thus, the foreseen domination of DSA as a legal certification tool is sufficiently important to focus research endeavours on the suitebility of this scheme to various sitnatic~s.In this paper, we prcsant s~x new DSA-based protocols for :9 Perforn~ng a quick batch-verification of, signatures. The proposed scheme allows to make the economy of = 450, modular multiplications. 9 Avoiding the cumbersome calculation of 1 / k rood q by the signer. 9 Compressing sets ofDSA transact/ons into shorter archive signatures. 9 Generating signatures from poe-calculated "Use & Throw" 224-bit signature-coupons. 9 Self-~.ertifying the moduli and bit-patterning directly q on p (gain of 60.4% in key size).All our schemes combine in a natural way full DSA compatibility and flexible U'ade-offs between computational complexity, transmission overheads and key sizes.

Abstract-Physical Unclonable Functions (PUFs) allow a silicon device to be authenticated based on its manufacturing variations using challenge/response evaluations. Popular realizations use linear additive functions as building blocks. Security is scaled up using non-linear mixing (e.g., adding XORs). Because the responses are physically derived and thus noisy, the resulting explosion in noise impacts both the adversary (which is desirable) as well as the verifier (which is undesirable). We present the first architecture for linear additive physical functions where the noise seen by the adversary and the noise seen by the verifier are bifurcated by using a randomized decimation technique and a novel response recovery method at an authentication verification server. We allow the adversary's noise ߟ a → 0.50 while keeping the verifier's noise ߟ v constant, using a parameter-based authentication modality that does not require explicit challenge/response pair storage at the server. We present supporting data using 28nm FPGA PUF noise results as well as machine learning attack results. We demonstrate that our architecture can also withstand recent side-channel attacks that filter the noise (to clean up training challenge/response labels) prior to machine learning.

Abstract-We describe a PUF design with integrated error correction that is robust to various layout implementations and achieves excellent and consistent results in each of the following four areas: Randomness, Uniqueness, Bias and Stability. 133 PUF devices in 0.13 µm technology encompassing seven circuit layout implementations were tested. The PUF-based key generation design achieved less than 0.58 ppm failure rates with 50%+ stability safety margin. 1.75M error correction blocks ran errorfree under worst-case V/T corners (±10% V, 125ºC/-65ºC) and under voltage extremes of ±20% V.All PUF devices demonstrated excellent NIST-random behavior (99 cumulative percentile), a criterion used to qualify random sources for use as keying material for cryptographic-grade applications.

Abstract. The design of usable yet secure systems raises crucial questions when it comes to balancing properly security and usability. Finding the right tradeoff between these two quality attributes is not an easy endeavor. In this paper, we introduce an original design model based on a novel usability inspection method. This new method, named Security Usability Symmetry (SUS), exploits automata machines theory and introduces the concept of an advanced Multifunction Teller Machine (MTM). We demonstrate, via case study, how to use this model during the design of secure, usable interactive systems.

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