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We present an electromagnetic-based method that enables prediction of microlithographic structures of 100 nm and below, for analyzing manufacturability of next-generation microchip technology in real time, in situ. The method is robust, versatile, precise, and fast, and experimentally verified by using both scanning electron microscopy and atomic force microscopy.

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In the fabrication of integrated circuits, device pattern size determines electrical performance characteristics. Variations in the size of lines, trenches, contacts, straps, etc. result in electrical device performance differences. When the variations occur from chip to chip or wafer to wafer, we find that entire chips function differently (e.g. impacts clock speeds). This paper discusses within-chip variations that can produce undesirable effects which, when severe enough, can kill an entire chip because portions of it have incompatible electrical performance. The modeling and characterization of image-size variations caused by lens aberrations of 5X photolithography steppers with lens field sizes from 1 5 2 to 22 mm2 are also discussed.