Power dissipation is rapidly becoming one of the most significant problems in IC design, and this in portables as well as ASIC and highperformance microprocessor platforms. In recent years, we have witnessed the emergence of a variety of design methods and design automation tools to keep dissipation within bounds. This might give the impression that power minimization is a solved issue, both from a design and a design automation perspective.Unfortunately, the truth is far from that. The next-generation designs are destined to be even more challenging from a power-dissipation perspective and novel solutions will be needed to meet the challenges. This in turn will require innovative EDA tools and methodologies.This panel, composed of designers, CAD managers and EDA manufacturers, addresses the most compelling issues in low-power lowenergy design automation, including what effectively works in the real-world and what does not. The discussion also focuses on what breakthroughs are needed for the next-generation designs.
Panelist Statements
Bill Bell -Texas Instruments, Dallas, TXIn the design era of system-on-a-chip and reusable Intellectual Property (IP) blocks, low-power design issues that were within our control are more difficult to resolve. Before, we could generally squeeze enough power out of the design by using special clock gating or lower level gate and transistor sizing methods to meet our goals. We cannot do this anymore since only a small portion of the power comes from our own IP. Now we have to rely on others (even inside your own company) to help meet our power goals.This drives two major issues that are not being adequately addressed. 1) The planning process for low-power design is as complicated if not more complicated than design planning for timing, yet no low-power design planning tools exist. 2) If we are going to have to rely on others for portions of our designs, then how are we going to communicate our power needs? We need standards for power control on IP. We need standards for specifying power usage, power constraints, power tests, power specs (peak power, RMS power, average power). These standards will help define the usage of power information in the tools in the process like routers, analysis tools, and synthesis tools.
Jerry Frenkil -Sente Inc., Chelmsford, MA
See embedded tutorial.
Vassilios Gerousis-Motorola Inc., Tempe, AZThe EDA industry has concentrated on power analysis tools, both in the areas of transistor, gate and RTL. Very few companies concentrate on RTL analysis. An evaluation of these tools will be presented at the panel. Very limited amount of work is done at the RTL level for power optimization. Only high-performance designers as well designers of battery-operated devices have concentrated on low-power designs (digital and analog) and EDA tools have not met their demands. Architectural-level tools for power optimization are still at the university laboratory stage.
Massoud Pedram-USC, Los Angeles, CAIt is widely recognized that efficient and accurate power estimation is ...
