It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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A metal–insulator–silicon (MIS) capacitor with hemi-spherical grained poly atomic layer deposition (ALD) deposited Al2O3 and multi-layered chemical vapor deposition (CVD) TiN structure is fabricated. The impact of the deposition process and post treatment condition on the MIS capacitor's time-dependent dielectric breakdown (TDDB) performance is also studied. With an optimized process, it is confirmed by Auger electron spectroscopy and secondary ion mass spectrometry analysis that the Al(CH3)3/O3-based ALD Al2O3 dielectric film is carbon free and the hydrogen content is as low as 9 × 1019 cm−3. The top electrode TiN is obtained by multi-layered TiCl4/NH3 CVD deposited TiN followed by 120 s post NH3 treatment after each layer. This has higher diffusion barrier in preventing impurity diffusion through TiN into the Al2O3 dielectric due to its smaller grain size. As shown in energy dispersive X-ray analysis, there is no chlorine residue in the MIS capacitor structure. The leakage current of the capacitor is lower than 1 × 10−12 A/cm2. No early failures under stress conditions are found in its TDDB test. The novel MIS capacitor is proven to have excellent reliability for advanced DRAM technology.

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