This paper presents a general strategy for the electrical performance and Signal Integrity assessment of electrically long multi-chip links. A black-box time-domain macromodel is first derived from tabulated frequency responses in scattering form. This model is structured as a combination of ideal delay terms with frequency-dependent rational coefficients. A new identification scheme is presented, based on an initial blind delay estimation process, followed by a refinement loop based on an iterative Delayed Vector Fitting (DVF) process. Two alternative passivity enforcement schemes based on local perturbations are then presented. The result is an accurate and guaranteed passive delay-based macromodel, which is synthesized as a SPICEcompatible netlist for channel analysis. The proposed procedure enables safe and reliable circuit-based transient simulations of complex multi-chip links, including nonlinear drivers and receivers. The performance of the proposed flow is demonstrated on a large number of channel benchmarks.

In this paper, we describe the challenging first-and secondlevel packaging technology of a new system packaging architecture for the IBM eServer z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

In this paper, we describe the first-and second-level system packaging structure of the IBM zEnterprise A 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power A blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

Data transmission on high-speed channels may be affected by several undesired effects, including coupling from nearby interconnects, dispersion, losses, signal reflections from terminations and from internal discontinuities, and nonlinear/dynamic effects of drivers and receivers. The latter are often neglected, leading to very fast solvers, whose results may, however, be questionable when driver/receiver nonlinearities are important. This paper presents a framework for the transient analysis of complex high-speed channels with arbitrary nonlinear termination circuits. The approach is based on decoupling channel and terminations through a scattering-based waveform relaxation (WR) formulation. The channels are here cast as delay-rational macromodels, which are solved in discrete time domain through fast delayed recursive convolutions. The terminations can be either arbitrary circuits, solved by SPICE, or nonlinear behavioral macromodels, which are here formulated in discrete-time scattering representations. To overcome the known convergence issues of standard WR methods, we apply here more general iterative solution schemes, such as generalized minimal residual and biconjugate gradient stabilized, integrated into inexact Newton iterations, obtaining a set of numerical schemes with guaranteed convergence. The excellent performance of the proposed approach is illustrated on a large set of benchmarks.

This paper introduces a scattering-based nonlinear macromodeling framework for high-speed differential drivers. Using an industrial test case, we show that the proposed scattering formulation enables more accurate and robust model identification with respect to standard voltage-current representations. The combination of proposed driver models with a Waveform Relaxation solver allows accurate and efficient transient channel simulation, including nonlinear and dynamic termination effects.