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Abstract-Advanced input queuing is an attractive, promising architecture for high-speed ATM switches, because it combines the low cost of input queuing with the high performance of output queuing. The need for scalable schedulers for advanced input queuing switch architectures has led to the development of efficient distributed scheduling algorithms.We introduce a new distributed scheduling algorithm, FIRM, which provides improved performance characteristics over alternative distributed algorithms. FIRM achieves saturation throughput 1 with lower delay than the most efficient alternative (up to 50% at high load). Furthermore, it provides improved fairness (it approximates FCFS) and tighter service guarantee than others. FIRM provides a basis for a class of distributed scheduling algorithms, many of which provide even more improved performance characteristics.

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Abstmct-We present a new scheduler, the two-dimenswnal round-robin (2DRR) scheduler, that provides high throughput and fair access in a packet switch that uses multiple input queues. We consider an architecture in which each input port maintains a separate queue for each output. In an .V x .V switch, our scheduler determines which of the queues in the total of .Y2 input queues are served during each time slot. We demonstrate the fairness properties of the 2DRR scheduler and compare its performance with that of the input and output queueing configurations showing that our scheme achieves the same saturation throughput as output queueing. The 2DRR scheduler can be implemented using simple logic components thereby allowing a very high-speed implementation. I. INTRODucTlONT HERE are many applications in the computer and communications tields that require the scheduling of a system (usually a switch) that has N input resources and iv output resources. This gives rise to a scheduling problem in which the resource requests can be represented by an N x N matrix RM, where RAf[R.('] = 1 indicates that there is at least one request for the Rth input and Cth output resource pair where R and C denote row and column indexes, respectively. During a time slot, only one request can be granted in any row or column of this request matrix since a given input or output resource can only serve one request per time slot. The scheduler determines which requests are satisfied during successive time slots. The objective of the scheduler is to provide high throughput, that is, to serve as many requests as possible, while also providing fair service to the different requests. The two-dimensional round-robin (2DRR) scheduler that is described in this paper satisfies these goals. The 2DRR algorithm can be efficiently used for any such scheduling problem with AT input and N output resources. Since we developed the algorithm for use in a high-speed switch, we focus on a switch application in the paper. One of the key characteristics of the 2DRR scheduling algorithm is that it allows an efficient hardware implementation so that it can be used in high-speed switches.A related scheduling problem has been discussed in the literature. In this related problem formulation, a o-aflc matri.r represents the aggregate demand for input/output pairs over a period of time slots. In a situation where the individual input queues to a switch have more than one request in them, the traffic matrix could be viewed as a tabulation of the queue contents for each inputioutput pair. This type of problem formulation is common in the area of satellite-switched timedivision-mukiple-access (SS/TDMA) systems [6]. A class of optimal algorithms (e.g., [6], [ 1I ], and references therein) have been developed to satisfy a given traffic matrix within X time slots where .Y is the maximum aggregate demand, from [he traffic matrix, on any input or output.Since the optimal scheduling algorithms are computationally expensive they do not lend themselves to high-speed switch applicat...

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