Ingestible electronics have revolutionized the standard of care for a variety of health conditions. Extending the capacity and safety of these devices, and reducing the costs of powering them, could enable broad deployment of prolonged monitoring systems for patients. Although prior biocompatible power harvesting systems for in vivo use have demonstrated short minute-long bursts of power from the stomach, not much is known about the capacity to power electronics in the longer term and throughout the gastrointestinal tract. Here, we report the design and operation of an energy-harvesting galvanic cell for continuous in vivo temperature sensing and wireless communication. The device delivered an average power of 0.23 μW per mm2 of electrode area for an average of 6.1 days of temperature measurements in the gastrointestinal tract of pigs. This power-harvesting cell has the capacity to provide power for prolonged periods of time to the next generation of ingestible electronic devices located in the gastrointestinal tract.

Two-dimensional electronics based on single-layer (SL) MoS offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

No abstract

Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection. [3,4], pulse frequency modulation (PFM) regulation logic, clock generator, gain selection block that include programmable low duty cycle timers, and a voltage reference. The transistor level implementation of the SC module is shown in Figure 21.7.2a which can be reconfigured for four gain settings (1-2/3-1/2-1/3) as shown in Fig. 21.7.2b. Each module consists of two charge transfer capacitors, 1nF each, and ten switches. Since the implementation of gain settings (2/3, 1/3) requires two capacitors while (1,1/2) can be achieved with one only, thus, for the latter each module is reconfigured into two identical sub-modules running with 180 degree phase shifted clocks for further ripple reduction.The losses due to the bottom plate parasitic capacitance of on-chip capacitors usually limit the peak efficiency of the converter. These losses occur as SC converters supply power to the load through the charge and discharge of flying capacitors (C 1 and C 2 ). A direct non-desirable impact to this process is the charge and discharge of the bottom plate parasitic capacitance, αC, every clock cycle [2]. As an example, for gain setting 1/2, the converter charges C 1 to (V in -V out ) in phase 1 and discharges it to V out in phase 2. In companion to this process the bottom plate capacitance gets charged to V out and discharged to ground wasting an energy of αC 1 V out 2 per cycle where α is technology dependent (the same process applied for capacitor C 2 but with the reverse order of phases). Highly efficient conversion is achieved by utilizing the ferroelectric capacitors, that posses extremely low bottom plate parasitics, for charge transfer. In addition, the architectures utilized for each gain setting are selected to minimize the voltage swing across the bottom plate capacitors for maximizing efficiency. Since the output load current is directly proportion...

No abstract