Physical unclonable function (PUF), a hardware that can extract the differences of the same implementations and provide unique secret keys without the utilization of non-volatile memory, is regarded as a promising security primitive in the near future. Ring Oscillator (RO) PUF is one of its easy silicon implementations, which exploits the frequency difference between a pair of structurally identical ring oscillators. However, a large number of ROs must be constructed if multiple stable output bits are required, which means unacceptable area overhead for lightweight applications. To solve this problem, configurable ROs using multiplexers and different delay units were proposed in previous papers. Unfortunately, most of them take advantage of the specific structure of a certain type of field-programmable gate arrays (FPGAs), thus not cost-saving for application-specific integrated circuit (ASIC). In this paper, we propose a configurable RO using only two hybrid logic gates in each stage for ASIC, which costs less area and power compared with previous proposals. Experiment on 50 FPGAs and one self-designed printed circuit board demonstrates satisfactory uniformity and uniqueness of this novel RO PUF. Furthermore, our proposal is proved to be reliable in a wide variety of environment conditions.

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Physical unclonable function (PUF) is a reliable physical security primitive. The Weak PUF and Strong PUF are two well-known PUF topologies. Strong PUF can be used to authenticate and protect intellectual property on FPGA chips. Classic PUF designs, like arbiter PUF, are hard to implement on FPGA and severely threatened by the machine learning based modeling attacks. In this work, we propose a new Strong PUF on FPGA by combining Weak PUF with obfuscation logic. Experiment results on a 28nm FPGA show that the resistance to modeling attack is good and the hardware overhead is small.

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