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<p><strong>Notice of Retraction</strong></p><p>-----------------------------------------------------------------------<br />After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles.<br /><br />We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.<br /><br />The presenting author of this paper has the option to appeal this decision by contacting ijres@iaesjournal.com.</p><p>-----------------------------------------------------------------------</p><p>Residue Number System (RNS) is a very old number system which was proposed in 1500 AD. Parallel nature for mathematical operations in RNS results in faster computation. This paper deals with designing of modulo multiplication in RNS. Direct computation of |AB|_m, requires multiplier to get A.B first and then Mod-m calculator to get the final result. We have used Vedic technique along with RNS to improve the computation time for modulo multiplication. This paper is aimed at designing and analysis of modulo multiplier for special moduli set like 3, 5 and 7. Comparative analysis in terms of area and delay is performed for input data size (N=8, 16 and 32-bit) between proposed technique and direct computation using Xilinx ISE 14.1. Design is also been compared using Synopsys Design Compiler with 32 nm Std_Cell Library. It is found that proposed technique is more efficient in terms of speed when input data size increases.</p>