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Interconnects are one of the main bottlenecks to circuit performance, with increasing importance in advanced technology nodes. With increased sensitivity of circuit delay to interconnect parasitics, we study the impact of process variation on interconnects. Based on GDSII-level layouts, we accurately study sources of systematic variability and quantify their repercussions on circuit performance in the ITRS 11 nm technology node. Additionally, we compare three lithography schemes and study their impact on interconnect capacitance and interconnect resistance. Consequently, we study the influence of interconnect RC on circuit performance. The study shows that, in multi-gate transistor technology, wire capacitance is less important in determining circuit delay, thus increasing tolerance of the circuit performance to the overlay variation in the litho-etchlitho-etch (LELE) lithography. We compare the LELE patterning with the self-aligned-double-patterning (SADP) , and show that it is more resistant to variability. We also show how the self-aligned-quadruple-patterning (SAQP) patterning impacts interconnect variability.