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A high-level partitioning methodology is introduced, which uses formulation-level discrete signal transform properties to provide improved results for their partitioning to distributed hardware architectures. We discuss how discrete signal transform characteristics were taken into account to focus design exploration during partitioning. Additionally, a description is given of the experiments conducted to determine the effect of formulation-level properties on solution quality. Perceived patterns in experimental results were used to generate 'partitionfriendly' formulations for distributed hardware architectures. I. INTRODUCTIONThe achievement of effective algorithm implementations to distributed hardware architectures (e.g multi-FPGA boards) is highly dependent on the process of partitioning. Most of the proposed high-level partitioning strategies apply generic local optimization techniques that miss out on alternate considerations which become apparent with knowledge of the algorithm's functionality [1]. Discrete signal transforms (DSTs) possess algorithmic level properties that have been used to manually obtain effective formulations for diverse computational architectures. Recently, methodologies such as FFTW and SPIRAL have been developed for the automated optimization of DST implementations to general purpose processor platforms [2] [3]. However, these methods have yet to be successfully adapted for automated partitioning methodologies on dedicated distributed hardware architectures (DHAs). The current trend toward reconfigurable computers and multicore systems-on-chip underlines the importance of developing effective partitioning techniques [4] [5].In our research we study the integration of properties such as symmetry, index mappings, and decomposition rules into automated partitioning strategies for DSTs to DHAs. We hypothesize that awareness of such characteristics during partitioning will result in a more focused exploration of the design space and improved solution quality. To this end, we designed a methodology that incorporates formulation-level transformations and other DST-derived strategies throughout the highlevel partition process [6]. In this paper, we describe our methodology, emphasizing how DST-specific considerations influence the implementation of our partition optimization heuristic. We also describe several experiments designed to understand the effect of DST formulation-level characteristics