As the technology nodes shrink, device makers are running into barriers with traditional post etch process flows. In the back-end-of-line (BEOL), the porous low-k materials can be damaged by the etch chemistries, the dry ash plasmas and the subsequent cleaning processes. Replacing the dry ash and typical wet cleaning processes with a one step selective solvent-based removal process can work to protect the etched low-k. The solvent-based blend must remove the reactive ion etch (RIE) residues and gap fill material used in the patterning step while preserving the low-k from further damage. This paper will focus on the removal of films and post etch residues in under 2 minutes with a novel solvent formulation.

Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them. In the area of electroplated solder applications, there has been widespread adoption of copper pillar bumps with lead free solder caps. Solder wetting of only the copper pillars after reflow confines the spread of the solder cap in the x,y plane enabling tighter pitch layouts, while the smaller solder cap still improves the robustness of the interconnection. However, as more data is gathered using this process, one area of growing interest is the characterization of polymer photoresist residue on the side walls of plated copper pillars with lead-free solder caps. As has been seen with other processes including for example, redistribution line (RDL) cleaning processes, cleaning challenges have increased in tighter pitch applications. In RDL, cleaning challenges were increased as cleaning processes that were once taken for granted were now being applied to wafers with 10μm line/space and tighter pitches. Analogies can be found in the tight pitch copper pillar cleans. Typical characterization techniques such as optical microscopy have been used traditionally in the industry as a post process inspection method. Advantages such as ease of use, fast throughput, automated tooling, use of filters to highlight certain defect types, and the ability to non-destructively inspect whole wafers have all contributed to its success in the field. With tighter pitch copper pillar applications, inspection using optical microscopy is challenged in an extreme and it is possible to inspect a clean copper pillar wafer and not see photoresist residue on the copper side walls. This paper will describe wet cleaning processes used today for copper pillar cleans, with special focus on characterization of the Cu pillar and solder side walls. Examples using several different photoresists and copper and solder configurations will be examined. Samples with differing copper/solder bump heights and pitches will be discussed. Cleaning and compatibility results will be shown.

The Bosch etch process is a critical process step used to create through silicon vias (TSVs) for 3D integrated circuit manufacturing. During the Bosch etch, a fluoropolymer passivation layer is formed on the sidewall of TSVs to help achieve a vertical profile and to protect the exposed dielectric materials. The fluoropolymer residue on the sidewalls in the TSVs must be removed prior to subsequent process steps. The highly fluorinated character of the fluorocarbon polymer residue makes its complete removal challenging due to characteristics such as limited solubility in solvents and slow or no reactivity with components of common cleaning or strip solutions. In this paper, the results of a study of solvents for developing formulations for removal of Bosch etch residue from TSVs are presented. The selection of components for an etch residue remover must take into consideration several key factors including removal efficiency, environmental-health-safety (EHS) guidelines, and material cost. The results demonstrate that the solvent selection has a dramatic impact on polymer removal efficiency, where poor solvent selection can lead to the formation of polymer balls inside the vias. The reported studies include cleaning results using a combination of polar solvents including protic and aprotic solvents, and amide and non-amide solvents. The cleaning performance is compared with a prediction using Hansen solubility parameters. Complete residue removal using TMAH-free and NMP-free formulations for TSV diameters down to 5 μm is demonstrated. Scanning electron microscopy, (SEM), energy-dispersive X-ray spectroscopy (EDS), and Auger electron spectroscopy (AES) were used to characterize the cleaning performance.

Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them. In the area of electroplated solder application, one area of growing interest is cleaning technology. There is a need for an integrated process to fabricate defect-free copper pillars with lead-free caps and lead-free solder plated bumps compatible with advanced packaging schemes and with improved yields and reliability. Photoresist removal and surface preparation have been identified as critical to the success. In familiar and widespread technology using 150 micropitch solder bumping, the introduction of RoHS rules for lead-free solder bump compositions, (SnAg, SnAgCu), proceeded in the absence of an integrated and tailored process capable of defect-free surface preparation. It was relatively simple for solder bump compositions in many devices to be converted to lead-free alloys. However, new challenges continue to arise in higher volume fabrication of SnAg micro-pillars (micro-pillars) or copper micro-pillars with lead-free solder caps as the bump pitch approaches 25 microm with aspect ratios of 1:1 or 1.5:1. Individual processes that are involved in the total integration, including (1) dielectric cleaning steps, (2) PVD seed Ti and Cu deposition, (3) electroplating, (4) thick photoresist application and patterning, (5) photoresist removal, (6) associated descum processes, and (7) copper seed metal etch steps, have been challenged to meet the demands. New geometries, higher aspect ratios and very dense solder bump arrays have created further challenges for these processes, stretching the older 150 microm technology beyond its capability. The focus of this paper is to identify a reliable route to defect-free copper micro-pillars with lead-free caps and lead-free solder plated micro-bumps after photoresist removal in applications compatible with advanced packaging schemes and with improved yields and reliability.