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A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

A vertically integrated latch-up based n-p-n bidirectional diode, which is analogous to an open-base bipolar junction transistor, is demonstrated for bipolar resistance-change memory selector application. A maximum current density of >50 MA/cm 2 and a selectivity of >10 4 are observed at a fast switching speed of within 10 ns. The high selectivity as a consequence of the sudden latch-up process is feasible owing to the positive-feedback process initiated by impact ionization. The optimization of the turn-on voltage is comprehensively investigated by numerical device simulation, which ensures the promising potential of the latch-up based selector device.

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