As an effort to improve the energy efficiency of switched-capacitor circuits, zero-crossingbased integrators (ZCBI) that consist of zero-crossing detectors and charging circuits have been proposed. To break the trade-off between accuracy and speed, ZCBI typically employs a two-phase charging scheme that relies on an additional threshold for zero-crossing detection. This paper proposes a simpler realization method of the two-phase charging scheme by means of charge sharing. To demonstrate feasibility of the proposed method, we designed and fabricated a second-order delta-sigma modulator in 180-nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results show that the modulator exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 46.3 dB over the bandwidth of 156 kHz with the power consumption of 684 µW. We also designed the same modulator in 65-nm CMOS technology and simulation results imply that the proposed circuit is able to achieve a much better energy efficiency in advanced technology.

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Zero-crossing-based integrators (ZCBIs) are energyefficient alternatives to conventional switched-capacitor integrators that are typically implemented using operational transconductance amplifiers (OTAs). However, ZCBIs suffer from signaldependent overshoot errors and increased dynamic power consumption due to inherent reset operation. This paper presents a ZCBI that employs a bidirectional two-phase charging scheme and performs the reset operation selectively. A 3rd-order Delta-Sigma modulator has been fabricated in a 28-nm CMOS technology using the proposed integrators. The prototype modulator achieves 67-dB SNR and 63-dB SNDR over the bandwidth of 196 kHz with an oversampling ratio of 64. It consumes 184 µW, which translates to the figure-of-merits of 154 dB (FoMs) and 390 fJ/conv-step (FoMw).

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