This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165[Formula: see text][Formula: see text]V rms at 60∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4[Formula: see text]mW from 1.2[Formula: see text]V power supply with a [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.048[Formula: see text]mm2, and the corresponding FoM is 27.2[Formula: see text]fJ/conversion-step at Nyquist rate.

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

In this paper, a high speed amplifier used in high-resolution GSPS pipelined ADC is described. To satisfy a 14bit 1GSPS ADC accuracy and speed demand, The high speed amplifier adopts two-stage Miller compensation architecture. To increase amplifier gain, active gain-boosted cascodes and cross-coupling positive feedback are used in the first stage of the amplifier. To improve phase margin and settling of the amplifier, big resistor and inductor are used in the second stage of the amplifier. The high speed amplifier used in a 14bit 1GSPS pipelined ADC fabricated on a 65nm CMOS process achieves a closed loop gain of 82dB, a closed bandwidth of 4.0GHz, phase margin of 70 degree, dissipates 250mW power, occupys 0.11mm 2 area.

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Although the scheme of designing transceiver with zero-IF architecture reduces the design cost, complexity and power loss of the system, this architecture is more sensitive to the I/Q mismatch problem existing in the analog front-end and it is difficult to eliminate the image interference caused by the mismatch. Therefore, a fast and low-cost I/Q imbalance calibration algorithm is needed. As for the problem of I/Q imbalance in zero-IF receiver, a blind estimation algorithm for extracting the calibration parameters and signal compensation is proposed because of the complexity of calculation and hardware circuit, as well as the power consumption of resources under the traditional algorithm. Based on the statistical property of the signal, this algorithm has the specific characteristics of low computational complexity and being easy to implement in hardware circuit. Due to different ideas of parameters extraction, a special calibration model is designed. The result of simulation shows that the proposed algorithm has not only better performance in compensation parameters estimation, but also better calibration performance than the traditional algorithm. By comparing the calibration performance in the case of different gain imbalances or phase imbalances, we can see that the algorithm can maintain a good calibration performance under different imbalance conditions.