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Parasitic oscillations in the rectifier diode voltage of phase-shifted-full-bridge (PSFB) converters limit their application in high-voltage and high-power situations. The conventional analysis method for parasitic oscillation in rectifier diode voltage in PSFB converters treats the filter inductor as a constant current source and fails to consider the impact of changes in filter inductor current on the rectifier diode’s parasitic oscillation. Consequently, this approach does not apply when analyzing the rectifier diode voltage’s parasitic oscillations in high-power PSFB converters employing an input-parallel output-series (IPOS) configuration with interleaved drive. This research paper introduces an innovative equivalent circuit model for analyzing the parasitic oscillations of rectifier diode voltage in IPOS high-power PSFB converters. The model takes into account the mutual influence of rectifier diode voltage oscillations between submodules under interleaved control, considering the influence of changes in filter inductor current on rectifier diode parasitic oscillation. Based on the circuit model, we explain the mechanism of multiple oscillations of the rectifier diode voltage and the reason for the high peak of the first oscillation. Consequently, the interplay of rectifier diode voltage oscillations in IPOS high-power k-module PSFB converters under interleaved control is analyzed. To mitigate the adverse effects of rectifier diode voltage parasitic oscillation, a buffering strategy involving the connection of a resistor capacitor diode (RCD) circuit in parallel after the rectifier bridge is adopted, considering the structure of the IPOS high-power PSFB converter. The study provides a detailed analysis of the circuit’s operation mechanism upon incorporating the RCD buffer circuit and establishes the relationship between buffer capacitance, resistance, and spike voltage. Furthermore, a design method for buffer capacitors and discharge resistors in buffer circuits is presented. Finally, a 100 kW prototype is tested to verify the rectifier diode voltage oscillation mechanism of the IPOS high-power PSFB converter and the rationality of the buffer capacitor and discharge resistor design method under the interleaved drive approach.

Compared with traditional controllers such as PI based on classic control theory, the article applies passive control (PBC) theory to the design of three-phase LCL grid-connected inverter controllers. The mathematical model of the system based on Euler-Lagrange (EL) is established, and the damping method of the trap is used to suppress the resonance spikes generated by the system, so that the system meets the requirements of grid connection. The simulation results verify the feasibility of the scheme.

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