A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.

A chiplet multi-objective optimization algorithm for 2.5-D integrated circuit (IC) based on a passive interposer is discussed in this article. Inspired by the network-on-chip mapping problem, we propose a novel algorithm, called chiplet multi-objective optimization, which minimizes the average temperature and the communication consumption between chiplets at the same time. The algorithm considers the specificities of 2.5-D IC chiplets, such as the spacing and different sizes of chiplets. In addition to the weight factor, α is also introduced to make a balance between temperature and the communication consumption. The designer can change the weight factor according to their own requirement. The multi-window display system is used as an example in this article to demonstrate the algorithm’s efficiency and the accuracy. According to our algorithm, the system temperature of the most ideal solution can be reduced by 8.34 K and the communication consumption reduced by 232.13 μJ.