The asymmetric saddle-shape warpage is one of the hardest limitations on the development of three-dimensional integrated circuits (3D ICs) as the vertical integration increases. To improve the product yield, an effective method for saddle-shape warpage reduction in 3D IC production by backside patterning laser annealing treatment with a multilayer structure is investigated in this work. The reduction of saddle–shaped warpage by patterning laser treatment is the first time in 3D NAND array wafer application and through simulations and experiments, the laser annealing pattern is determined. In addition, the materials of the multilayer structure are selected as amorphous Al2O3 and TiN according to experiments and theoretical analysis. As a result, a conformal 47.8 µm optimization of the saddle-shape warpage is successfully reached in a control wafer test by patterning laser annealing treatment.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.