Canon Litho Products support Vertical Lithography challenges required by TSV and advanced packaging applications that support “More-than-Moore” advancements. Vertical Lithography challenges include accurately performing backside, infrared alignment to distorted bonded-wafer grids and imaging through thick resist films. This paper will provide examples illustrating severe wafer distortion that can be experienced after wafer thinning and the impact of overlay and imaging control. This paper will also introduce Canon stepper features that are designed to address Vertical Lithography challenges including the Canon Through-Silicon Alignment (TSA) System and advanced Projection Lens. Grid distortion characterization data and stepper compensation results are presented to illustrate Canon stepper technology performance under severe process conditions.

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.

Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid error due to die placement errors.

Heterogeneous Integration of logic, memory, photonic, analog and other value-adding functions is one approach for increasing electronic system efficiency, performance and bandwidth while helping reduce overall manufacturing costs. To capitalize on Heterogeneous Integration benefits, designers are requiring finer resolution Redistribution Layer patterning and larger package sizes to maximize System-in-Package integration possibilities. Production of large-package electronics systems is well-suited for Panel Level Packaging (PLP) and achieving uniform submicron patterning across the entire rectangular panel is a key lithography challenge. To meet this challenge, Canon developed the first lithography exposure system or stepper that is capable of achieving submicron resolution on 500 mm panels. The stepper features a panel handling system for processing panels up to 515 mm x 515 mm in size and is also equipped with wide-field projection lens featuring a maximum 0.24 Numerical Aperture and a large 52 mm x 68 mm image field. This paper will report on evaluation results for a submicron PLP process using the panel stepper and will introduce high-resolution PLP process challenges including warped panel handling. Process results on Copper Clad Laminate (CCL) substrates will be reported including pattern uniformity, adjacent shot stitching accuracy and overlay accuracy on substrates containing die-placement error that is common in Fan-Out processes.

Advanced process technology is required to develop and enable mass production of high-density 3D and 2.5D interconnect technologies. In this paper, Canon and IBM @ Albany NanoTech will present process optimization results for lithography applications requiring precise thick-resist profile control and precise overlay accuracy of distorted patterns on bonded process wafers. Canon will also provide additional product updates from Canon Anelva.