Chemical-mechanical polishing (CMP) has emerged as the dominant dielectric planarization method due to its ability to reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation in polished oxide thickness across typical chips, which can impact circuit performance and yield. A comprehensive semiphysical pattern dependent model of the CMP process, integrated with a parameter extraction and process characterization methodology, has been developed to enable accurate and efficient prediction of post-CMP oxide thickness across patterned chips. First, in the characterization phase, test wafers are polished to obtain model parameters for the desired CMP process. Standard test layouts have been defined which consist of regions with different feature density and pitch; a new contribution is the inclusion of "step density" structures which provide large abrupt post-CMP thickness variations to improve parameter extraction. The key extracted parameter which characterizes the particular CMP process is the planarization length; we propose a definition of planarization length as the characteristic length of an elliptic weighting function based on the long range pad deformation and pressure distribution during CMP. Second, in the modeling phase, a pattern density dependent analytic model is used to predict temporal film thickness evolution. The elliptic weighting function with a known planarization length is used to calculate an average or effective pattern density across the product chip of interest. A fast Fourier transform (FFT) calculation enables efficient computation of the effective density based on deposition-biased underlying local layout densities. Given the effective density, the remaining oxide thickness after CMP is computed, highlighting regions suffering from over-or under-polish. The methodology is demonstrated for a production CMP process. Extracted planarization lengths are between 2.55 and 3.58 mm for representative processes, with root mean square fitting error of 306 A. Prediction of post-CMP oxide thickness on a product chip demonstrates 260 A root-mean-square fitting error, or less than 3% of the removed oxide thickness.

Variation is a key concern in semiconductor manufacturing and is manifest in several forms. Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies. Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation. Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed. In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer-die interaction contributions to spatial variation. Waferlevel estimation methods include filtering, spline, and regression based approaches. Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods; important issues include spectral interpolation and sampling requirements. Finally, the interaction between wafer-and die-level effects is important to fully capture and separate systematic versus random variation; spline-and frequency-based methods are proposed for this modeling. Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits.

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrialbased experiments demonstrate the beneficial impact of metalfill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation. Index Terms-Chemical-mechanical polishing (CMP), design for manufacturing, metal-fill, within-die variation. I. INTRODUCTION I N recent years, chemical-mechanical polishing (CMP) has emerged as the primary technique for planarizing interlayer dielectrics [1], [2]. Although CMP is very effective at reducing the as-deposited step height and achieves a measure of global planarization not possible with either spin-on or resist etchback Manuscript

We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect delay and clock skew in both aluminum and copper interconnect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD variation has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations.

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role.